The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique which can be effectively used for the manufacturing of high frequency power amplifier which is mainly comprised of hetero junction bipolar transistors (HBT) which constitute ultrahigh-speed IC elements.
As a semiconductor device which exhibits high speed performance and low power consumption performance, a hetero junction bipolar transistor (hereinafter also referred to as HBT) has been known. This hetero junction bipolar transistor is used in a form that the transistor is incorporated into a high frequency power amplifier (RF power amplifying module) of a mobile communication terminal such as a portable cellular phone.
The HBT has a structure in which a sub-collector layer and a collector layer are sequentially laminated onto one surface (main surface) of a semiconductor substrate, a base layer is partially formed over the collector layer, and an emitter layer which is formed of a semiconductor having a wide band gap is partially formed over the base layer.
In a power amplifying device for transmission in a communication system, the HBT has now been used as a transistor. Such a semiconductor device is described in Japanese Laid-open Patent 210723/2001.
In Japanese Laid-open Patent 210723/2001, a technique for manufacturing a semiconductor device having a bias circuit which suppresses a change of an idle current attributed to a temperature change of a power transistor Tr1 is disclosed. Such a semiconductor device is manufactured using a GaAs substrate as a base and, for compensating for a temperature shift of the idle current, a plurality of Schottky diodes are provided to a base inputting part. The bias circuit is constituted of two transistors (Tr2, Tr3) which are connected to the power transistor Tr1, two Schottky diodes (D1, D2) and three resisters (R1 to R3).
That is, a base terminal of the power transistor Tr1 is connected to a collector terminal of the transistor Tr2 through a resistor R3 in an emitter follower method, and a base terminal of the transistor Tr2 is grounded through the transistor Tr3 which short-circuits a base and a collector of the Schottky diodes D1, D2 thus suppressing the change of the idle current C of the transistor Tr1 which is generated when the temperature changes.
Further, with respect to this semiconductor device, base electrodes and the Schottky electrodes of the HBT are simultaneously formed at the time of manufacturing the semiconductor device.
On the other hand, in the manufacturing of the HBT, for preventing an excessive etching of the sub-collector layer, there has been known a technique which provides an InGaP layer between the sub-collector layer and the collector layer. This technique is described in IEEE Electron Device Lett., vol. 18, p355, 1997.
Further, in IEEE Electron Device Lett., vol. 18, p559, 1997, there is disclosed a technique which enhances the isolation performance by arranging an undoped InGaP layer having a resistance higher than a resistance of an undoped GaAs layer below a collector layer.
As a transistor which constitutes a high frequency power amplifier (RF power module) for a mobile communication unit, a hetero junction bipolar transistor (HBT) which constitutes a ultra high-speed IC element has been used. Further, to compensate for a temperature shifting of an idle current in the transistor, a bias circuit which provides a plurality of Schottky diodes to a base inputting part is incorporated. Resistance elements are also incorporated in this bias circuit.
The reduction of manufacturing cost has been requested with respect to the HBT in the same manner as other transistors and modules. With respect to the power transistor into which the bias circuit is incorporated, as described in the above-mentioned literature, there has been proposed the method which simultaneously forms the Schottky electrodes and the base electrodes using a same material.
To explain manufacturing steps thereof, as shown in FIG. 23(a), a semiconductor layer (n+ type GaAs layer) below an emitter electrode 56 is etched using the emitter electrode 56 as a mask until the etching reaches a surface of a semiconductor layer (n type InGaP layer) which constitutes a wide gap emitter layer 54 below the semiconductor layer (n+ type GaAs layer) thus forming a mesa-shaped emitter layer 55.
Thereafter, an etching mask not shown in the drawing is formed and, as shown in FIG. 23(a), using this etching mask as a mask, a semiconductor layer which constitutes the wide gap emitter layer 54 which is exposed in a periphery of the emitter layer 55, a semiconductor layer (p-type GaAs layer) which constitutes a base layer 53 below the semiconductor layer, and a semiconductor layer (n+ type GaAs layer) 52a which constitutes a collector layer below the base layer 53 are sequentially etched, wherein the semiconductor layer 52a is etched to an intermediate depth thereof, thus forming the base layer having a mesa shape (mesa-shaped base layer) 53.
Subsequently, a base electrode 57 and a Schottky electrode 58 are simultaneously formed, wherein the base electrode 57 is formed over the wide gap emitter layer 54 in the periphery of the emitter layer 55 and the Schottky electrode 58 is formed over the semiconductor layer (n+ type GaAs layer) 52a which constitutes a collector layer in a Schottky diode forming region which is disposed away from a region where the HBT is formed. The base electrode 57 is subjected to an alloying treatment (heating treatment).
As a result, the wide gap emitter layer 54 below the base electrode 57 is alloyed so that a base electrode 57 and the base layer 53 are electrically connected to each other.
Further, in the manufacturing of the HBT, as shown in FIG. 23(a), a substrate (wafer) which is eventually produced by sequentially forming respective semiconductor layers consisting of a sub collector layer 51, the collector layer 52, the mesa-shaped base layer 53, the wide gap emitter layer 54 and the emitter 55 over one surface (main surface) of a semi-insulation GaAs substrate 50 is used.
However, in the method which forms the base electrode over the semiconductor layer which constitutes the wide gap emitter layer 54, it is necessary to form holes for forming the base electrode in the etching mask. Accordingly, in view of the mask alignment tolerance for forming this hole, it is necessary to ensure the mask alignment tolerance length between an outer periphery of the base electrode 57 and an outer periphery of a mesa-shaped base layer 53 in FIG. 23(b). As a result, a junction area between the base layer 53 and the collector layer 52 is increased. The increase of the area between the base and the collector deteriorates the high frequency characteristics (for example, maximum oscillation frequency f max).
Then, as shown in FIG. 24, when the mask alignment tolerance length is shortened, the outer periphery of the base electrode 57 extends beyond the periphery of the mesa-shaped base layer 53 and is brought into contact with the collector layer 52 (contact portion 70) thus giving rise to a short-circuit defect. This leads to the lowering of a yield factor and brings about a drawback that a manufacturing cost is pushed up.
To prevent the outer periphery of the base electrode 57 from extending beyond the mesa-shaped base layer 53 and coming into contact with the semiconductor layer (n+ type GaAs layer) 52a which constitutes the collector layer, it is necessary to ensure a minimum mask alignment tolerance length xe2x80x9caxe2x80x9d. FIG. 25 is a schematic view for showing the size relationship among respective portions in the manufacturing of the HBT while ensuring the mask alignment tolerance length xe2x80x9caxe2x80x9d.
A base-collector junction length L2 is a length which is obtained by adding 2xc3x97mask alignment tolerance length xe2x80x9caxe2x80x9d to a distance (distance between outer peripheries) xe2x80x9cbxe2x80x9d between one outer periphery of the base electrode 57 and another outer periphery which is disposed opposite to one outer periphery of the base electrode 57 and hence, the high frequency power amplifier becomes large-sized. The distance between outer peripheries (xe2x80x9cbxe2x80x9d) is a sum of a width xe2x80x9cdxe2x80x9d of the base electrode 57, a length xe2x80x9ccxe2x80x9d of the emitter electrode 56 and a distance xe2x80x9cexe2x80x9d from a periphery of the emitter electrode 56 to an inner periphery of the base electrode 57.
The inventors of the present invention have studied the above-mentioned distances and widths from a viewpoint of miniaturization of the HBT element and have obtained following sizes of respective portions as a result of the study. That is, the lengths and the widths are set such that c=4 xcexcm, d=1 xcexcm, e=1 xcexcm and b=8 xcexcm. Further, by setting the mask alignment tolerance length xe2x80x9caxe2x80x9d as a=0.8 xcexcm, the base-collector junction length L2 becomes 9.6 xcexcm.
On the other hand, to ensure the insulation separation (isolation) between the HBT and the other element arranged close to the HBT, there has been known a structure which provides a separation groove between the elements by etching. In performing this etching, when the etching is insufficient, the separation groove is not formed thus giving rise to a short-circuit defect, while when the etching is excessive, a large stepped portion is formed and hence, a line which is arranged traversing the stepped portion is disconnected due to the large stepped portion.
FIG. 26 is a schematic view showing an example of a defect caused by the insufficient etching or the excessive etching. For example, an area inside a left frame in FIG. 26 constitutes a region A for forming the HBT and an area inside a right frame in FIG. 26 constitutes a region B for forming another element such as a Schottky diode, for example. In the region A for forming the HBT, lines xe2x80x9caxe2x80x9d to xe2x80x9ccxe2x80x9d which are respectively connected to an emitter electrode E, a base electrode B and a collector electrode C traverse the separation groove, while in the region B for forming the Schottky diode, a line xe2x80x9cdxe2x80x9d which is connected to a Schottky electrode st traverses the separation groove.
When the etching becomes insufficient in the formation of the separation groove, there arises a case that a defective isolation is generated between the region A for forming the HBT and the region B for forming the Schottky diode as indicated by (1) in FIG. 26. Further, when the etching is excessive, a stepped portion of the separation groove at the periphery of the region A for forming the HBT or the periphery of the region B for forming the Schottky diode is enlarged and hence, the line xe2x80x9caxe2x80x9d, the line xe2x80x9ccxe2x80x9d or the line xe2x80x9cdxe2x80x9d is disconnected at the stepped portion as indicated by (2) in FIG. 26. Further, when the stepped portion is large, in forming the lines by etching, the etching of the portion which is arranged along the stepped portion can not be performed favorably and hence, a metal layer for forming the line remains as indicated by (3) in FIG. 26. The lines which are arranged closed to each other are connected due to this residual metal h thus giving rise to a short-circuit defect. Such an excessive or insufficient etching lowers a manufacturing yield factor thus pushing up a product cost.
Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which can achieve the enhancement of a yield factor as well as the reduction of a manufacturing cost.
It is another object of the present invention to provide a method for manufacturing a semiconductor device which exhibits the excellent high frequency characteristics and can be manufactured at a low cost by narrowing an area between a base and collector in a hetero junction bipolar transistor.
The above-mentioned and other objects and novel features of the present invention will become apparent from the description of this specification and attached drawings.
To briefly explain the summary of typical inventions described in the inventions disclosed in the present application, they are as follows.
(1) In a method for manufacturing a semiconductor device in which a plurality of semiconductor layers are sequentially formed in a laminated manner over a semiconductor substrate, a hetero junction bipolar transistor, a Schottky diode and a resistance element are formed in a monolithic manner, and a separation groove for establishing an electric insulation is formed at least between the hetero junction bipolar transistor and the Schottky diode,
respective semiconductor layers which are formed into a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of the semiconductor substrate and, thereafter,
in the manufacture of the hetero junction bipolar transistor, among the above-mentioned respective semiconductor layers, given semiconductor layers are formed in given patterns by sequential etching thus sequentially forming an emitter layer, a wide gap emitter layer, a base layer, a collector layer and a sub collector layer, and at the same time, an emitter electrode is formed over the emitter layer, an alloying treatment is applied to the wide gap emitter layer which extends around the emitter layer thus forming a base electrode which is electrically connected to the base layer, and a collector electrode is formed over the collector layer which extends around the base layer thus forming the hetero junction bipolar transistor,
in the manufacture of the Schottky diode, a Schottky electrode is formed over a semiconductor layer corresponding to the collector layer, and an ohmic electrode for diode is formed over a semiconductor layer corresponding to the sub collector layer thus forming the Schottky diode,
in the manufacture of the resistance element, a resistance film is formed over an insulation film in a region outside a region where the hetero junction bipolar transistor and the Schottky diode are formed, and
the Schottky electrode and the resistance film are simultaneously formed using a same material.
Further, the semiconductor substrate is formed of a semi-insulating GaAs substrate, the sub collector layer is formed of a first conductive-type GaAs layer, the collector layer is formed of a first conductive-type GaAs layer, the base layer is formed of a second conductive-type GaAs layer, the wide gap emitter layer is formed of a first conductive-type InGaP layer, the emitter layer is formed of a first conductive type GaAs layer having an InGaAs layer as a surface layer thereof, the etching stopper layer is formed of a first conductive-type InGaP layer. The Schottky electrode and the resistance film are made of alloy which mainly contains a high melting-point material or a silicide and have given portions on which lines made of aluminum are overlapped.
Due to such a constitution, the Schottky diode and the resistance film can be formed simultaneously and hence, man-hours can be reduced so that a product cost can be reduced.
(2) In the above-mentioned constitution (1), the base electrode is formed such that the base electrode surrounds the emitter layer and, at the same time, a region ranging from the base electrode to the inside of the base electrode except for an outer periphery of the base electrode is covered with a mask for etching, and the collector layer is etched to an intermediate depth thereof using the mask for etching and the base electrode as masks thus forming the mesa-shaped base layer. Due to such a constitution, it is possible to reduce a base-collector junction area so that the high frequency characteristics (for example, maximum oscillation frequency fmax and the like) of the hetero junction bipolar transistor can be enhanced.
(3) In the above-mentioned constitution (1), an etching stopper layer which is formed of a material having an etching speed lower than an etching speed of the sub collector layer is formed between the semiconductor substrate and the sub collector layer and, at the same time, an etching stopper layer which is formed of a material having an etching speed lower than an etching speed of the collector layer is formed between the sub collector layer and the collector layer,
an etching which is performed to expose the sub collector layer by etching the collector layer is completed by stopping the etching at the etching stopper layer, and
the formation of the separation groove includes an etching treatment in which etching of the sub collector layer is stopped at the etching stopper layer, an etching treatment in which the etching stopper layer is etched, and an etching treatment in which a surface layer portion of the semiconductor substrate is etched. Due to such a constitution, it is possible to prevent a shortage of etching and an excessive etching and so that an isolation defect attributed to the shortage of etching can be suppressed and a disconnection of lines or a short-circuit between lines which occurs at a stepped portion attributed to the excessive etching can be prevented whereby a manufacturing yield factor is enhanced and a production cost can be reduced. This constitution (3) is particularly effective (a) when it is necessary to lower the resistance of the sub collector by increasing a thickness of the sub collector layer and (b) when it is necessary to increase a collector breakdown strength and to reduce a collector capacitance by increasing a thickness of the collector layer. For example, with respect to a GaAs HBT for power use, a sub collector layer and a collector layer whose total thickness is equal to or more than 1 xcexcm are usually used.